(a) Field of the Invention
The present invention relates to a semiconductor device including an NMOSFET and a method for manufacturing the same, more in detail, to the semiconductor device including the NMOSFET having an accurate threshold voltage at a designed value due to excellent controllability of the threshold voltage, and reduced p-n junction leakage current, and the method for manufacturing the same.
(b) Description of the Related Art
A high performance LSI has been realized which includes a CMOSFET including an n-channel MOSFET and a p-channel MOSFET. Reduction of the length of the channels of the MOSFET and the resulting shallower junction of the source/drain region are progressing.
In order to form a shallower source/drain junction in an n-channel MOS transistor, ions having a smaller thermal diffusion coefficient during heat treatment and activation thereof are used as n-type impurities for ion-implantation.
Heretofore, arsenic (As) having a smaller thermal diffusion coefficient compared to phosphorous (P) is ion-implanted and the wafer is heat-treated to form the boundary of the source/drain diffusion regions located at a designed shallower position.
Referring now to FIGS. 1A and 1B, a conventional method of forming a source/drain region of an NMOSFET by means of ion-implantation of arsenic will be described.
At first, element isolation regions 64 are formed in a p-type silicon substrate 62. Then, a p-well 66 is formed in a field region isolated by the element isolation regions 64, and a p-channel region 68 for controlling a threshold voltage is formed by boron (B) implantation. A gate oxide layer 70 is formed on the p-channel region 68, and a gate electrode 72 made by polysilicon is formed thereon. Then, n-type extension regions 74 are formed along the p-channel region 68, and side walls 76 made of insulator is formed along the gate electrode 72.
In accordance with these procedures, a semiconductor device shown in FIG. 1A can be obtained.
Then, arsenic ions as n-type impurities are implanted at an acceleration energy of 50 keV and a dosage of 5×1015/cm2. The wafer is then heat-treated for activation, to form n-type source/drain regions 78 thereby providing the semiconductor device shown in FIG. 1B.
In the conventional method for forming the source/drain region of the NMOSFET, a reverse short channel effect of the NMOSFET is noticeable which lowers the controllability of the threshold voltage. The reverse short channel effect is a phenomenon in which the threshold voltage largely changes depending on the length of the gate wherein the threshold voltage increases with reduction of the gate length and the reduction of the gate length below a specified value rapidly lowers the threshold voltage as shown in FIG. 2.
FIG. 2 is a graph showing relations between gate lengths (μm) plotted on abscissa and threshold voltages (V) plotted on ordinate by using an ion species, an acceleration energy and an ion dosage as parameters. Lines (1), (2) and (3) in the graph indicate the relations between the gate length and the threshold voltage when the arsenic ions are implanted at the acceleration energies of 50 keV, 30 keV and 10 keV, respectively, and at the fixed dosage of 5×1015/cm2.
The reverse short channel effect largely changes the threshold voltage even by the slight change of the gate length during manufacture of the NMOSFET. When, for example, the gate length is only slightly shortened in the step for forming the gate electrode whereby the control of the threshold voltage of the MOSFET is hardly performed, the threshold voltage is significantly increased. The inability of manufacturing the NMOSFET having the specified threshold voltage is a bar to elevating a production yield of semiconductor devices.